1. Technical Field
The present invention relates to a voltage regulator, and more particularly, to a non-isolated current-mode-controlled switching voltage regulator that regulates an input DC voltage to output a constant DC voltage while switching control mode between PWM mode and VFM mode depending on a current output to load circuitry.
2. Discussion of the Background
With currently increasing concern for environmental and ecological issues, there is a growing need for energy-saving electronic devices, particularly those operating with battery-based power supply. Two common approaches to conserving energy in electronic equipment are to reduce power consumed by functional units of the electronic device, and to improve efficiency and reduce energy loss of power circuitry supplying the electronic device.
A non-isolated switching voltage regulator is an example of a high-efficiency power source used in small portable electronic devices, in which an output transistor switches on and off current flow to temporarily store an input energy in an inductor and release the stored energy at a constant voltage higher or lower than that of the input energy.
One major technique used to control operation of a switching voltage regulator is pulse width modulation (PWM) control, which adjusts an ON time or duty cycle of a switching transistor with a clock signal having a constant frequency and a variable pulse width or pulse duration. Another control technique commonly used is variable frequency modulation (VFM) control, also referred to as pulse frequency modulation (PFM) control, which adjusts a switching frequency of a switching transistor with a clock signal having a variable frequency and a constant pulse duration. Some VFM control schemes vary a clock frequency seamlessly using a variable oscillator, and others create a variable-frequency signal by skipping pulses in an original pulse train oscillating at a constant frequency.
Typically, power consumed by a switching voltage regulator is proportional to the switching frequency with which a switching transistor is operated. The fact indicates that with low power supplied to load circuitry, PWM control is less efficient in terms of power consumption than VFM control, since the former constantly switches the output transistor at a fixed frequency whereas the latter can adjust the switching frequency to decrease corresponding to the low-load condition. On the other hand, VFM control is inferior to its counterpart in terms of operational stability, for varying the switching frequency can cause noise and ripple in the output of the voltage regulator.
To combine the advantages of PWM control and VFM control to obtain high power efficiency, some conventional voltage regulators incorporate dual-control mode power supply circuitry that can switch control mode between PWM mode and VFM mode according to the load condition.
FIG. 1 is a circuit diagram illustrating a conventional switching voltage regulator 100 employing PWM and VFM control modes.
As shown in FIG. 1, the voltage regulator 100 is a step-down or buck DC-DC converter with synchronous rectification, which converts a voltage Vin input to an input terminal IN to output a constant voltage Vout to an output terminal OUT for supply to a load circuit 120.
The voltage regulator 100 has an output stage formed of a switching transistor M101 and a synchronous rectifier transistor M102, the former being a P-channel metal-oxide semiconductor (PMOS) transistor and the latter an N-channel metal-oxide semiconductor (NMOS) transistor, with a node LX therebetween connected to an inductor L101 and an output capacitor Co.
The voltage regulator 101 has control circuitry including a pair of voltage sensing resistors R101 and R102, a first reference voltage generator 102, an error amplifier 103, a first comparator 104, a current/voltage converter 110, a slope voltage generator 111, an adder circuit 112, a second voltage generator 107, a second comparator 108, an oscillator 109, a reset-set (RS) flip-flop 105, and an inverter or switching controller 106.
In the voltage regulator 101, the output transistors M101 and M102 are connected in series between the input terminal IN and a ground GND, with the node LX therebetween connected to the inductor L101. The inductor L1 is connected between the node LX and the output terminal OUT, and the capacitor Co is connected between the output terminal OUT and the ground GND. The output terminal OUT is connected to the load circuit 120 as well as to the current/voltage converter 110.
The resistors R101 and R102 are connected in series between the output terminal OUT and the ground GND to form a voltage divider. The error amplifier 103 has an inverting input connected to the voltage divider, a non-inverting input connected to the first voltage generator 102, and an output connected to the first and second comparators 104 and 108.
The voltage divider resistors R1 and R2 output a feedback voltage Vfb proportional to the output voltage Vout, while the first voltage generator 102 outputs a first reference voltage Vr1 for comparison with the feedback voltage Vfb. Based on a difference between the two input voltages Vfb and Vr1, the error amplifier 103 outputs an amplified error voltage Ve at its output terminal, which increases as the output voltage Vout decreases, and decreases as the output voltage Vout increases.
The current/voltage converter 110 is connected to the inductor node LX. The adder circuit 112 is connected between the current/voltage converter 110 and the slope voltage generator 111. The comparator 104 has an inverting input connected to the output of the error amplifier 103, and a non-inverting input connected to the adder circuit 112.
The current/voltage converter 110 generates a current-sensing voltage Vsen by amplifying a difference between the input voltage Vin and a nodal voltage VLX at the inducer node LX. The amplified voltage Vsen is proportional to the inductor current iL.
The slope voltage generator 111 generates a sawtooth slope voltage Vslp for addition to the current-sensing voltage Vsen. The slope voltage Vslp is added to the current-sensing voltage Vsen by the adder circuit 12 to generate a ramp voltage Vc substantially proportional to the inductor current iL.
The first comparator 104 compares the voltages Vc and Ve against each other to generate a pulse width modulation signal Spwm for output to the driver circuit DRV, which goes high when the voltage Vc exceeds Ve, and low when the voltage Vc falls to Ve or below.
The second comparator 108 has an inverting input connected to the error amplifier 103, a non-inverting input connected to the second reference voltage generator 107, and an output connected to the oscillator circuit 109.
The second reference voltage generator 7 generates a second reference voltage Vr2 for comparison with the error voltage Ve. By comparing the error amplifier output Ve against the reference voltage Vr2, the comparator 108 generates an oscillator enable signal OSCEN for output to the oscillator circuit 109, which goes low when the voltage Ve exceeds Vr2, and high when the voltage Ve falls to Vr2 or below.
The oscillator circuit 109 provides a clock signal CLK to the driver circuit DRV depending on the status of the enable signal OSCEN.
The RS flip-flop 105 has a reset or “R” input connected to the first comparator 104, and a set or “S” input connected to the oscillator circuit 109, and a non-inverting or “Q” output connected to the controller 106. The controller 106 has a first input In connected to the flip-flop Q output, a second input Lx connected to the inductor node LX, a first output P connected to the gate of the switching transistor M101, and a second output N connected to the gate of the synchronous rectifier transistor M102.
Receiving the pulse signal Spwm at the R input and the clock signal CLK at the S input, the RS flip-flop 105 causes its Q output to go high when the signal CLK goes high, and to go low when the signal Spwm goes high. The switching controller 106 provides first and second control signals PHS and NLS, respectively, to control operation of the respective transistors M101 and M102 according to the status of the first and second input terminals In and Lx.
In such a configuration, the voltage regulator 100 can control operation of the switching transistor M1 either in VFM mode or in PWM mode depending on a current iout output to the load circuit 120.
FIG. 2 is a timing diagram showing waveforms of the signals in the voltage regulator 100 operating in VFM mode and in PWM mode.
During operation in VFM control mode, the output current iout supplied to the load 120 is relatively low, so that the error voltage Ve generally remains below the second reference voltage Vr2. In this mode, the smaller the output current iout, the faster the output voltage Vout increases and the error voltage Ve decreases, resulting in a shorter period of time during which the switching transistor M101 remains on. On the other hand, the smaller the output current iout, the slower the output voltage Vout decreases, resulting in a longer period of time during which the switching transistor M101 remains off. With an output current sufficiently small, this results in a longer time interval and a smaller frequency with which the switching transistor M101 turns on.
The voltage regulator 100 switches control mode from VFM mode to PWM mode when the output current iout increases to raise the switching frequency, maintaining the error voltage Ve higher than the second reference voltage Vr2.
During operation in PWM mode control, the output current iout supplied to the load 120 is relatively high, so that the error voltage Ve generally remains above the second reference voltage Vr2. Thus, the output OSCEN of the second voltage comparator circuit VC2 remains low to cause the oscillator circuit OSC to output a periodic pulse clock signal CLK oscillating at a constant frequency.
When the clock signal CLK goes high, the RS flip-flop 105 sets the Q output from low to high, so that the switching controller 106 causes the switching transistor M101 to turn on and the synchronous rectifier transistor M102 to turn off. This causes a current iL to flow into the inductor L101 from the input terminal IN, the amount of which increases in proportion to a difference between the input and output voltages Vin and Vout.
At the same time, the adder circuit 112 outputs a ramp voltage Vc by adding a slope voltage Vslp to a voltage Vsen proportional to the inductor current iL, which increases from the ground level GND in accordance with the increase in the inductor current iL.
When the voltage Vc exceeds the error voltage Ve, the output Spwm of the first comparator 104 goes from low to high, causing the RS flip-flop 105 to reset the Q output from high to low. In response to the first input In going low, the controller 106 applies high voltage signals PHS and NLS to the gates of the corresponding transistors, thereby causing the switching transistor M101 to turn off and the synchronous rectifier transistor M102 to turn on.
With the switching transistor M101 thus shut off, the ramp voltage Vc falls to the ground voltage GND, resulting in the output Spwm of the first comparator 104 going from high to low. As the transistor M101 shut off no longer connects the input terminal IN to the inductor node LX, the inductor 101L draws a current iL from the ground GND through the synchronous rectifier transistor M102, the amount of which gradually decreases in proportion to the output voltage Vout.
Before the inductor current iL falls to zero, the oscillator circuit 109 outputs another pulse CLK to start another operational cycle of the voltage regulator 101.
During operation in PWM control mode described above, the greater the output current iout, the shorter the period of time during which the switching transistor M101 remains on. In order for the voltage regulator to smoothly change its control mode, properly setting the inductor current iL during transition from VFM mode to PWM mode is important.
FIG. 3 shows waveforms of the inductor current iL in the voltage regulator 100 during transition from VFM mode to PWM mode with the output current iout transitioning from below to above a critical current ia with which the switching regulator enters from discontinuous operation to continuous operation.
In FIG. 3, the waveform iLa represents the inductor current measured when the VFM/PWM transition occurs at time ta where the output current iout is below the critical current ia so that the voltage regulator 100 operates in discontinuous mode. In this case, switching control mode from VFM to PWM abruptly raises the switching frequency of the transistor M101 and hence the energy supplied to the inductor L101, resulting in a steep surge in the output voltage Vout. The abnormal rise of the output voltage Vout continues until time tb at which the output current iout is increased to the critical current ia so that the voltage regulator 100 enters continuous mode operation.
The waveform iLc represents the inductor current measured when the VFM/PWM transition occurs at time tc where the output current iout is increased above the critical current ia after the voltage regulator 100 enters continuous mode operation. In this case, while the voltage regulator 100 operates in continuous mode, the switching transistor 101 controlled in VFM mode ends one switching cycle prematurely before the inductor current iLc returns to the baseline level, resulting in the inductor current iLc becoming improperly high in the subsequent switching cycle. The improperly high inductor current iLc excessively increases the output voltage Vout to extend the duration of the switching cycle, which in turn excessively decreases the output voltage Vout during the long switching cycle.
The waveform iLb represents the inductor current measured when the VFM/PWM transition occurs at time tb. In contrast to the other cases, under this condition, the voltage regulator 100 can smoothly switch from VFM to PWM control mode without causing anomalies in the output voltage Vout. The measurements indicate that synchronizing transition from VFM to PWM control mode with the output current iout reaching the critical current ia effects stable operation of a dual-control mode switching voltage regulator.
In addition, the cases described in FIG. 3 differ in the amount of current supplied to the inductor L101 per one switching cycle during VFM mode operation. Increasing the inductor current per switching cycle can improve power efficiency in VFM mode operation, since it reduces switching frequency of the output transistor which is proportional to the amount of power consumed by the voltage regulator. However, as can be seen from the fluctuations in the waveform iLc, this involves the risk of destabilizing voltage regulation during transition from VFM mode to PWM mode.
Several techniques have been proposed to determine the timing at which a dual-control mode switching transistor switches the control mode from VFM mode to PWM mode.
For example, one conventional method proposes a voltage regulator that determines the timing for control mode transition according to a result of comparing duty cycles of a drive signal of a switching transistor, an output signal of a PWM comparator, and a variable frequency clock signal. According to this method, the duty cycle of each control signal is transformed to a proportional voltage, based on which comparator circuitry compares the duty cycle of the clock signal against those of the PWM signal and the clock signal to switch the control mode according to the comparison results.
Another conventional method provides a voltage regulator that adjusts a PWM control signal when the PWM control signal has a pulse width smaller than that of a VFM control signal. According to this method, a differential signal generator generates a signal indicating a difference between the PWM pulse width and VFM pulse width. The differential signal is input to a variable frequency oscillator that controls frequency of a reference signal used to generate the PWM control signal.
A drawback common to the conventional methods described above is that complicated and bulky circuitry is required for timing determination. That is, the former method involves separate signal converters to transform the three control signals, as well as voltage comparators to compare the transformed signals, while the latter includes the differential signal generator and the variable oscillator, which may require several electronic components. Moreover, both of the conventional methods fail to take into account the power efficiency during VFM control mode operation.
Thus, what is needed is a simple and power-efficient dual-control mode voltage regulator that can smoothly switch control mode from VFM to PWM without causing variations in the output voltage.